1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a silicide layer without a short circuit between a gate electrode and a diffusion layer and between diffusion layers.
2. Description of the Related Art
In recent years, elements in a semiconductor integrated circuit such as an LSI have been formed by a fine processing technique for high integration. For example, an impurity diffusion layer of a source region or a drain region is formed to be shallow in depth and small in area. Further, a wiring pattern for connecting elements is also formed to have a small width. For this reason, the resistance of the impurity diffusion layer and wiring pattern increases preventing high speed operation of the elements. For this reason, a silicide layer of refractory metal, especially, a silicide layer of Ti formed on the surface of an impurity diffusion layer in semiconductor devices have been used to reduce the resistance of the impurity diffusion layer. Thus, high speed operation can be accomplished.
A method is disclosed in U.S. Pat. No. 4,855,798, in which the Ti silicide layer is formed in self-alignment manner. This method of forming the Ti silicide layer in a self-alignment manner will be described with reference to FIGS. 1A to 1G.
First, as shown in FIG. 1A, a field oxide film 2, a gate oxide film 4, a gate electrode 3 and sidewall films 5 are formed on a semiconductor substrate 1. Impurity ions are implanted into exposed portions of the silicon. substrate 1 to form diffusion layers.
Next, as shown in FIG. 1B, a protection oxide film 7 for the impurity ion implantation is formed on the whole surface of the substrate 1 by, for example, a CVD method. Then, impurity ions 8 are implanted to form diffusion layers 9. Subsequently, heat treatment is performed at a temperature equal to or more than 900.degree. C. to activate the implanted impurity ions.
Next, as shown in FIG. 1C, the protection oxide film 7 is removed and a natural oxide film on each of the diffusion layers 9 is removed before the sputtering of Ti.
Next, as shown in FIG. 1D, a Ti film 10 is formed on the whole surface of the substrate 1 by, for example, the sputtering method. The Ti film 10 is heat-treated in an inert gas ambience, e.g., in a nitrogen ambience at a temperature equal to or less than 700.degree. C., to form Ti silicide layers 11 of C49 phase which are TiSi.sub.2 having high resistance (first sintering process). At this time, the Ti silicide layers 11 are formed only on the gate electrode 3 and the diffusion layers 9 in a self-alignment manner, as shown in FIG. 1E.
Next, as shown in FIG. 1F, a part of the film 10 of non-reacted Ti is removed from the field oxide film 2 and the sidewall films 5. Then, further heat treatment is performed at a temperature equal to or more than 800.degree. C. As a result, as shown in FIG. 1G, the silicide layers 11 are converted into Ti silicide layers 12 of C54 phase which is TiSi.sub.2 having low resistance (second sintering process).
However, in the above-mentioned method, there is a problem in that a short circuit is easily formed between the gate electrode and the source region, and between the diffusion layers, when the finer processing is applied to the elements and then the Ti silicide layer is formed. This short circuit is formed due to the extension of the Ti silicide layer or generation of conductive material onto the region where the Ti silicide layer should not be originally formed. In other words, since the Ti silicide layer is formed on the field oxide film for separating between the diffusion layers and the sidewall film for separating the gate electrode and the diffusion layer, the short circuit is formed between them.
When the etching time of the non-reacted Ti film is elongated to remove the extension of the Ti silicide layer on the field oxidation film or the sidewall film or the conductive material, the Ti silicide layer is also etched. As a result, a new problem occurs in which the resistance of the diffusion layer increases.
Therefore, methods are proposed to prevent the extension of the Ti silicide layer onto the region where the Ti silicide layer should be not formed.
The first conventional example of these methods is described in Japanese Laid Open Patent Disclosure (JP-A-Showa 61-150216). In this method, after a Ti film is formed on a silicon substrate, a first silicide reaction is performed at a relative low temperature of 400 to 600.degree. C. Then, a non-reactive portion of the Ti film is removed and the Ti silicide layers of high resistance are formed on the diffusion layers and a gate electrode. Subsequently, a second sintering process is performed at a temperature of equal to or higher than 800.degree. C. to convert the Ti silicide layer of high resistance into the Ti silicide layer of low resistance. Because the temperature in the first sintering process is low, the extension of the Ti silicide layer can be prevented.
Also, a second conventional example of the above methods is described in Japanese Laid Open Patent Disclosure (JP-A-Showa 59-126672). The second convention example is shown in FIG. 2. In this method, for the purpose of preventing the extension of a Ti silicide layer on a sidewall film or the reaction of the sidewall film and the Ti film, the sidewall film is formed of a SiN film, making it difficult to cause a reaction with the Ti film.
In the methods described above, however, the following new problem is caused. That is, in the method shown in the first conventional example, there is the problem in that a desired resistance cannot be accomplished when finer processing is applied to the diffusion layer or the gate electrode. This is because the layer resistance of the diffusion layer after the second sintering process cannot be set below the desired resistance value, since the temperature of the first sintering process is low so that the resistance of the Ti silicide layer is high.
When the temperature of the second sintering process is raised to create a diffusion layer resistance below the desired resistance value, there is a problem in that Ti elements of the silicide layer cohere. For this reason, when the temperature of the first sintering process is decreased, even if the extension of the Ti silicide layer can be restrained, a low diffusion layer resistance can not be achieved.
Also, in the second conventional example, there is a problem in that although the short circuit between the gate electrode and the diffusion layer can be prevented, the short circuit between the diffusion layers cannot be restrained.
In this manner, the short circuit between the gate electrode and the diffusion layer and between the diffusion layers can not be completely restrained using the conventional methods.